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CXA2542AR
RF Signal Processing Servo Amplifier for CD Player
Description The CXA2542AR is a bipolar IC developed for CD player RF signal processing and servo control. Features * Automatic focus bias adjustment circuit * Automatic tracking balance and gain adjustment circuits * RF level control circuit * Interruption countermeasure circuit * Anti-shock circuit * Defect detection and prevention circuits * RF I-V amplifier, RF amplifier * APC circuit * Focus and tracking error amplifier * Focus, tracking and sled servo control circuits * Focus OK circuit * Mirror detection circuit * Single power supply and dual power supplies Applications CD players Structure Bipolar silicon monolithic IC 48 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC 12 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1400 mW Recommended Operating Conditions Operating supply voltage VCC - VEE 3.0 to 3.6 V 4.5 to 5.5 V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E98743-PS
CXA2542AR
Block Diagram
RF_M
RFTC
RF_O
RF_I
36
35
34
33 VCC
32
31
30
29
28
27
CC1
LD
CB
26
25
VCC VEE VCC
PD1 IV AMP
VEE VEE VEE RF SUMMING AMP
PD2 37 PD2 IV AMP
FOK
PD
CP
CC2
PD1
VCC APC VEE
24 SENS2
F 38 F IV AMP VCC E 39 IFB1
LASER POWER CONTROL
VCC VCC
IIL TTL
23 SENS1
FE AMP
IFB4
IFB2
E IV AMP BAL1 BAL2 BAL3 BAL4
IFB3
IFB5
IFB6
FO. BIAS WINDOW COMP.
VEE
22
C. OUT
INT VEE 40 VEE TOG1 TOG2 VEE LEVEL S VEE TOG3 TOG4 VCC MIRR 21 XRST VEE IIL TTL 20 TRK. GAIN WINDOW COMP. E-F BALANCE WINDOW COMP. FOH FOL TGH TGL BALH BALL ATSC TZC FZC DFCT TM1 TDFCT 45 TG1 VCC VCC VC 46 TM4 VEE VCC FZC 47 TM7 VCC FZC COMP. FEO 48 FOCUS PHASE COMPENSATION FS1 TM3 VEE TM5 VEE TM2 13 SL_P 14 SL_M TM6 VCC 15 SL_O TRACKING PHASE COMPENSATION DFCTO IFB1-6 BAL1-4 TOG1-4 FS1-4 TG1-2 TM1-7 PS1-4 ISET 16 ISET FOK TTL IIL TGFL LPCL MIRR XDFCT1 DFCT2 LPC CC1 19 XLT DATA
TGFL
TEO 41
LPFI 42
LDON
ATSC 43
ATSC WINDOW COMP. TZC 44 TZC COMP.
IIL DATA REGISTER INPUT SHIFT REGISTER ADDRESS DECODER SENS SELECTOR OUTPUT DECODER VCC
18
CLK
17
VCC
FS2 DFCT FS4 TG2
FSET
VEE
1 FEI
2 FDFCT
3 FGD
4 FLB
5 FE_O
6 FE_M
7 SRCH
8 TGU
9 TG2
10 FSET
11 TA_M
12 TA_O
-2-
CXA2542AR
Pin Description Pin No. Symbol I/O Equivalent circuit Description
1
FEI
I
1
147 100k 147
Focus error input.
2
FDFCT
I
2
3
Connects the capacitor for defect time constant.
3
FGD
I
3
147
68k
Ground this pin through a capacitor for cutting the focus servo highfrequency gain.
4
130k
40k
330k 470k
4
FLB
I
4
External time constant setting pin for boosting the focus servo lowfrequency.
5
FE_O
O
Focus drive output.
5
12
TA_O
O
12 15
Tracking drive output.
15
SL_O
O
250
Sled drive output.
147
90k
6
FE_M
I
6 50k 2
Focus amplifier inverted input.
147
7
SRCH
I
7 50k
20k 11
External time constant setting pin for generating the focus search waveform.
-3-
CXA2542AR
Pin No.
Symbol
I/O
Equivalent circuit
Description
110k
8
TGU
I
147 20k 8
423k 82k
External time constant setting pin for switching the tracking high-frequency gain.
9
TG2
I
9 470k
External time constant setting pin for switching the tracking high-frequency gain.
147k
10
FSET
I
10 15k 15k
Peak frequency setting pin for focus and tracking phase compensation amplifier.
100k
11
147
TA_M
I
11 11
Tracking amplifier inverted input.
13
SL_P
I
147 13 2
Sled amplifier non-inverted input.
147
14
SL_M
I
14 22
Sled amplifier inverted input.
16
ISET
I
147 16 50
Connect the external resistor to set the current which determines the Focus search, Track jump, and Sled kick levels.
-4-
CXA2542AR
Pin No. 17
Symbol
I/O
Equivalent circuit
Description
VCC
I
17
VCC
Positive power supply.
18
CLK
I
147 18 20 1k
20
Serial data transfer clock input from CPU. (no pull-up resistance)
20
DATA
I
Serial data input from CPU. (no pull-up resistance)
19
XLT
I
147 19 21 2.5p 4k
20
Latch input from CPU. (no pull-up resistance)
21
XRST
I
Reset input; resets at Low. (no pull-up resistance)
22
C. OUT
O
22 23 24 20k 147
Track number count signal output. Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the command from CPU.
100k
23
SENS1
O
24
SENS2
O
Outputs DFCT2, MIRR, BALL, TGL, FOL, and others according to the command from the CPU.
20k 147
25
FOK
O
25
40k
Focus OK comparator output.
100k
-5-
CXA2542AR
Pin No.
Symbol
I/O
Equivalent circuit
Description
75k 147 26 43k 39k
26
CC2
I
Input for the RF summing amplifier output with capacitance coupled.
147
28
CB
I
28 7.6k 240k
Connects the defect bottom hold capacitor.
29 100k
29
CP
I
1.5k
Connects the MIRR hold capacitor. MIRR comparator non-inverted input.
30
RF_I
I
Input for the RF summing amplifier output with capacitance coupled.
147 30
31
RF_O
O
RF summing amplifier output. Eyepattern check point.
147 31 147 32 10k 27 147 10k
32
RF_M
I
RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin. RF summing amplifier output. Used for the defect capacitance coupling.
27
CC1
O
147
50
33
RFTC
I
33 50 10
External time constant setting pin during RF level control.
-6-
CXA2542AR
Pin No.
Symbol
I/O
Equivalent circuit
Description
10k
34
LD
O
1k 34
APC amplifier output.
20 8
35
PD
I
147 35
55k 10k
APC amplifier input.
10k 0.2p 2k
8k
36 37
PD1 PD2
I I
147 36 37 100 8.65k
RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins.
12p 260k
38 39
F E
I I
147 38 39 10 500
F I-V and E I-V amplifier inverted input. Connect these pins to photo diodes F and E pins.
40
VEE
--
40
VEE
Negative power supply.
-7-
CXA2542AR
Pin No.
Symbol
I/O
Equivalent circuit
Description
41
TEO
O
41
147
15k 32k 15k 6.6k 3k 150k 20k 150k
Tracking error amplifier output. E-F signal is output.
100k
45
TDFCT
I
45
147 3
Connects the capacitor for defect time constant.
42
LPFI
I
147 42
Comparator input for balance adjustment. (Input from TEO through LPF)
7
1k
100k
43
ATSC
I
147 43 100k 10 10 1k
Window comparator input for ATSC detection.
10 147
44
TZC
I
44 75k
Tracking zero-cross comparator input.
-8-
CXA2542AR
Pin No.
Symbol
I/O
Equivalent circuit
Description
46
VC
O
50 46
120 120
15k
(VCC + VEE)/2 DC voltage output.
VC
147
54k 7
47
FZC
I
47 6k 300k
Focus zero-cross comparator input.
10 25p 147
48
FEO
O
48 174k 300 10
Focus error amplifier output. Connected internally to the window comparator input for bias adjustment.
-9-
CXA2542AR
Electrical Characteristics
TEST T1 T2 T3 T4 RF amplifier T5 T6 T7 T8 T9 T10 T11 T12 T13 FE amplifier T14 T15 T16 T17 T18 T19 T20 Item Current consumption 1 Current consumption 2 Center amplifier output offset Offset Voltage gain 10, 13 SW conditions (ON switches) 19 (OFF) 19 (OFF) 19 (OFF) SD RST RST RST RST RST RST RST 39F 39F 39F 39F 39F 39F 3BF 3BE 3BD 3BB 3B7 3AF 39F 37 36 48 48 48 48 48 48 48 48 48 36 37 36 37 36 37 36 37 Input pin 17 40 -- Measurement pin 17 40 46 31 31 31 31 48 48 48
(VCC = 1.5V, VEE = 1.5V, Topr = 25C)
Measurement conditions Min. 12.0 Typ. 18.5 Max. 25.0 Unit mA mA mV mV dB V V mV dB dB dB V V mV mV dB dB dB dB dB
-25.0 -18.5 -12.0 -100 -70 1kHz I/O ratio V2 = 0.2VDC V2 = 0.2VDC 1FB6: ON 1kHz I/O ratio 1kHz I/O ratio 16.5 1.2 -- -120 15.6 15.6 -3 V2 = 100mVDC V2 = 100mVDC IFB1, 2, 3, 4, 5, 6: OFF IFB1: ON, BIAS0: reference
IFB2: ON, BIAS0: reference Output gain difference with T15 IFB3: ON, BIAS0: reference Output gain difference with V17 IFB4: ON, BIAS0: reference Output gain difference with V18 IFB5: ON, BIAS0: reference Output gain difference with V19 IFB6: ON, BIAS0: reference Output gain difference with V20
0 -13 19.5 1.4 -1.3 0 18.6 18.6 0 1.4 -1.3 718
100 70 22.5 -- -1.0 120 21.6 21.6 3 -- -1 1042
Max. output 10, 13 amplitude - High Max. output amplitude - Low Offset Voltage gain 1 10 Voltage gain 2 13 Voltage gain difference Max. output 13 voltage - High Max. output voltage - Low BIAS0 BIAS1 BIAS2 BIAS3 BIAS4 BIAS5 BIAS6 10 10, 13
1 -- 560
-29.0 -22.7 -16.5 5 5 5 5 5 6 6 6 6 6 7 7 7 7 7
- 10 -
CXA2542AR
TEST
Item FOH threshold value FOL threshold value Offset GAIN UP (F) GAIN UP (E) Voltage gain F0 Voltage gain F1 Voltage gain F2 Voltage gain F3 Voltage gain F4 Voltage gain E0 Voltage gain E1 Voltage gain E2 Voltage gain E3 Voltage gain E4
SW conditions (ON switches)
SD
Input pin
Measurement pin 48
Measurement conditions IFB6: ON
Pin 1 voltage when SENS1 (Pin 23) goes from High to Low IFB6: ON
Min.
Typ.
Max.
Unit
FE amplifier
T21
39F
5
20
35
mV
T22
39F 34F 308 14 15 14 14 14 14 14 15 15 15 15 15 36F 308 36F 308 34F 34E 30F 34D 34B 347 34F 30F 00 30E 30D 30B 307 34F 308 34F 308 3C4 3C4 3C4 3C4 3C0 38 39 38 39 38 38 38 38 38 39 39 39 39 39 38 39 35 35 35 35 35
48
Pin 1 voltage when SENS2 (Pin 24) goes from High to Low
-35
-20
-5
mV
T23 T24 T25 T26 T27 T28 T29 TE amplifier T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 APC T40 T41 T42
41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 34 34 34 34 34
TOG: OFF, BAL1, 2, 3: ON V1 = 2 kHz, I/O ratio TOG: OFF, BAL1, 2, 3: ON V1 = 2 kHz, I/O ratio TOG: OFF, BAL1, 2, 3: ON V1 = 2kHz, TOG: OFF I/O ratio V1 = 2kHz, TOG1: ON Reference to F0 V1 = 2kHz, TOG2: ON Reference to F0 V1 = 2kHz, TOG3: ON Reference to F0 V1 = 2kHz, TOG4: ON Reference to F0 V1 = 2kHz, BAL: OFF I/O ratio V1 = 2kHz, BAL1: ON Reference to E0 V1 = 2kHz, BAL2: ON Reference to E0 V1 = 2kHz, BAL3: ON Reference to E0 V1 = 2kHz, BAL4: ON Reference to E0 V1 = 1VDC, TOG: OFF, BAL1, 2, 3: ON V1 = 1VDC, TOG: OFF, BAL1, 2, 3: ON I1 = 364A I1 = 439A I1 = 515A 0.8mA sink I1 = 515A, LD: OFF
-25 7.2 7.2 1.2 -2.3 -3.9 -6.9
0 10.2 10.2 4.2 -1.8 -3.4 -6.4
25 13.2 13.2 7.2 -1.3 -2.9 -5.9
mV dB dB dB dB dB dB dB dB dB dB dB dB V V mV mV mV mV V
-11.1 -10.6 -10.1 -1.6 0.16 0.58 1.43 2.96 0.5 -- 1.4 0.46 0.88 1.73 3.26 0.7 -0.8 4.4 0.76 1.18 2.03 3.56 -- -0.5
Max. output 1 voltage - High Max. output voltage - Low Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 9 4 LD OFF 1
-900 -704 -500 -693 -293 163 -200 1.1 613 132 1.3 107 1063 500 --
- 11 -
CXA2542AR
TEST T43 RF level controll T44 T45 T46 T47 T48 T49 Focus servo T50 T51 T52 T53 T54 T55 T56 T57 T58 Tracking servo T59 T60 T61 T62 T63 T64
Item 50% limit 30% limit -50% limit -30% limit DC voltage gain FCS total gain Feed through 1
SW conditions (ON switches) 8 8 10, 13 10, 13 1
SD 3C7 3C5 3C7 3C5 08 --
Input pin 35 30 35 30 35 36 37 35 36 37 1 -- 1 47 1 1 -- -- 38 -- 38 38 38
Measurement pin 34 34 34 34 5 -- 5 47 5 5 5 5 12 -- 12 12 12 12 12
Measurement conditions
I1 = 273A Output difference with LPC ON/OFF I1 = 333A Output difference with LPC ON/OFF I1 = 742A Output difference with LPC ON/OFF I1 = 667A Output difference with LPC ON/OFF
Min. 725 315
Typ.
Max.
Unit mV mV mV mV dB dB dB mV V V mV mV dB dB dB V V mV mV mV mV mV
1330 1935 915 1515
-1421 -816 -211 -1215 -615 17.4 20.9 39.5 -- 150 1.3 -1.3 -15 24.4 41.5 -30 177 -- -1
T9 + T47
I/O gain difference between SD = 00 and SD = 08 Pin 47 voltage when SENS1 (Pin 23) goes from Low to High
37.5 -- 123 1 --
1
00 08 00 08 08 02 03 25 -- 20 25 20 25 20 25 2C 28 10 10 20
FZC threshold 20 value Max. output 1 voltage - High Max. output voltage - Low Search voltage (-) Search voltage (+) DC voltage gain TRK total gain Feed through 1 Max. output voltage - High Max. output voltage - Low Jump output voltage (-) Jump output voltage (+) ATSC threshold 5, 17 value (-) ATSC threshold 5, 17 value (+) TZC threshold 18 value 1
V1 = 200mVDC V1 = -200mVDC
-721 -581 -441 399 DC gain between TEO and TA_O T26 + T55
I/O gain difference between SD = 20 and SD = 25.
539 14.6 18.8 -- 1.3 -1.3
679 17.8 20.8 -39 -- -1
11.4 16.8 -- 1 --
V1 = -0.3VDC V1 = 0.3VDC
-652 -512 -372 437
Input voltage when TG2 (Pin 9) goes from Vcc/2 to Vcc Input voltage when TG2 (Pin 9) goes from Vcc/2 to Vcc
577 -15 15 0
717 -7 25 20
43 43 44
43 43 44
-25 7 -20
Pin 44 voltage when SENS1 (Pin 23) is 0V
- 12 -
CXA2542AR
TEST T65 Tracking servo T66 T67 T68 FOK T69 T70 T71 Sled servo T72 T73 T74 T75 T76 MIRROR T77 T78 T79 T80 T81 T82
Item
BAL COMP threshold value - High BAL COMP threshold value - Low GAIN COMP threshold value - High GAIN COMP threshold value - Low
SW conditions (ON switches) 16 16 14 14
SD 300 300 308 34F 308 34F -- 25 20 25 25 25 20 20
Input pin 42 42 38 38 30 13 13 13 13 -- -- 30 30 30 36 37 36 37 36 37 36 37
Measurement pin 42 42 41 41 25 15 15 15 15 15 15 24 24 24 23 23 23 23
Measurement conditions
Pin 42 voltage when SENS1 (Pin 23) goes from High to Low Pin 42 voltage when SENS2 (Pin 24) goes from High to Low Pin 41 voltage when SENS1 (Pin 23) goes from High to Low Pin 41 voltage when SENS2 (Pin 24) goes from Low to High
Min. 5 -35 168 127
Typ. 20 -20 193 145
Max. 35 -5 218 163
Unit mV mV mV mV mV dB dB V V mV mV kHz Vp-p Vp-p kHz kHz Vp-p Vp-p
FOK threshold value 8 Voltage gain Feed through 6, 7 6
Pin 30 voltage when Pin 25 is 0V V1 = 100Hz, I/O ratio I/O gain difference between
SD = 20 and SD = 25.
-560 -510 -450 50 -- 1 -- -- -- 1.3 -1.3 -- -34 -- -1
Max. output voltage - High 6 Max. output voltage - Low Kick voltage 1 Kick voltage 2
Max. operating frequency 1
Min. input operating voltage 1 Max. input operating voltage 1
V1 = 400mVDC V1 = 400mVDC REV x 1 FWD x 1 Measures at SENS2 pin. Measures at SENS2 pin. Measures at SENS2 pin. Measures at SENS1 pin. Measures at SENS1 pin. Measures at SENS1 pin. Measures at SENS1 pin.
6
-750 -600 -450 450 30 -- 1.8 -- 2.5 -- 1.6 600 -- -- -- -- -- -- -- 750 -- 0.3 -- 1 -- 0.5 --
8 8 8 10, 11, 12, 13 10, 11, 12, 13 10, 11, 12, 13 10, 11, 12, 13
20 20 20 10 10 10 10
Min. operating frequency 1
DEFECT
Max. operating frequency 1
Min. input operating voltage 1 Max. input operating voltage 1
- 13 -
Electrical Characteristics Measurement Circuit
R6 240k VCC VEE GND GND GND GND R14 10k S8 R13 30k 31 30 29 28 25 27 26 C6 C7 0.01 0.01 R19 10k C9 0.068 VCC R5 240k S12 AC S10 36 DC R7 34k R4 34k R8 R10 330 1M C5 1 S9 35 32 33 34 S11 I1 0A VCC VEE I2 0.8mA
V2
LD
PD1
CC1
CC2
RFTC
RF_M
RF_O
RF_I
FOK
S13 R22 10k VCC R21 10k 38 F R1 390k S15 R20 10k 39 E C2 33 40 VEE XRST 21 DATA 20 XLT 19 CLK 18 GND Vcc 17 ISET 16 SL_O 15 SL_M 14 SL_P 13 S7 C11 47 C10 33 R26 120k R23 60k R25 13k GND R24 5.1k 47 FZC GND 48 FEO GND 41 TEO S16 42 LPFI S17 43 ATSC S18 CLK VCC VEE XLT R26 100k DATA C. OUT 22 VCC XRST SENS1 23 VCC 37 PD2 SENS2 24 R2 390k S14
GND
GND
VEE
GND
GND
FGD
FEI
FLB
FE_M
TGU
FSET
FDFCT
SRCH
TG2
TA_M
R3 10k 1 2 3 S3 S1 S2 R9 47k GND 4 5 6
FE_O
TA_O
- 14 -
44 TZC C1 1000P GND 45 TDFCT S19 GND 46 VC S20 7 8 9 10 11 12 S5 R15 10k C4 R12 0.1 100k R11 13k R16 510k R17 100k C8 0.01 VCC GND GND GND C3 1000P GND VCC
GND
GND
PD
CP
CB
GND S6
V1
R18 13k GND
AC
DC
CXA2542AR
GND
CXA2542AR
Application Circuit 1 (2.5V power supply)
1 Vcc 1k 3.3 A C B D 37 PD2 F E VEE 38 F 39 E 40 VEE 41 TEO 100k 0.01 0.047 330k 0.022 0.1 46 VC 47 FZC 150k 42 LPFI 0.01 43 ATSC 47k 470p 44 TZC 45 TDFCT 36 VEE 500 100
Vcc 22 100
LD 10H PD VEE VEE 1M 1 30k 0.01 0.033 0.01 0.068 MICRO COMPUTER DSP
35
34
33
32
31
30
29
28
27
26
25
PD
RF_I
PD1
CP
RF_O
RF_M
RFTC
SENS2 24 SENS1 23 C. OUT 22 XRST 21 DATA 20 XLT 19 CLK 18 Vcc 17 60k ISET 16 SL_O 15 SL_M 14 100k VEE DRIVER 0.015 8.2k 13 3.3 22 15k Vcc
FDFCT
0.022 48 FEO
SRCH
FE_M
FE_O
1 10k 10k 2200p
2 3 680k 0.1
4
5 0.1
6
7
8 4.7
9
TA_M
11
TGU
FLB
FEI
FSET
FGD
10
TA_O
TG2
12 82k
100k 510k 0.015 Vcc DRIVER
100k 0.1 DRIVER
0.033
Application Circuit 2 (Single +5V power supply)
Vcc 1 Vcc 1k 3.3 A C B D 37 PD2 F E 38 F 39 E 40 VEE 41 TEO 100k 0.01 0.047 330k 0.022 Vcc 10 10 47 FZC SL_M 14 150k 42 LPFI 0.01 43 ATSC 47k 470p 0.1 45 TDFCT 46 VC ISET 16 SL_O 15 100k DRIVER 0.015 8.2k 13 3.3 22 15k 44 TZC CLK 18 Vcc 17 60k Vcc XLT 19 36 35 34 33 32 31 30 29 28 27 26 25 500 100 1M 1 30k 0.01 0.033 0.01 0.068 MICRO COMPUTER DSP 22 100
LD 10H PD
RF_O
RF_M
RFTC
RF_I
PD1
CC1
CC2 TA_M
11
PD
CP
CB
LD
SENS2 24 SENS1 23 C. OUT 22 XRST 21 DATA 20
FDFCT
0.022 48 FEO
SRCH
FE_M
FSET
FE_O
1 10k 10k
2 3 0.1 680k 2200p
4
5 0.1
6
7
8 4.7
9
10 510k
TA_O
FGD
TGU
TG2
FLB
FEI
FOK
12 82k
100k 0.015
0.1
100k DRIVER
0.033 Vcc
DRIVER
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 15 -
FOK
CC1
CC2
CB
LD
SL_P
SL_P
CXA2542AR
Description of Functions RF Amplifier The photodiode currents input to the input pins (PD1 and PD2) are each I-V converted through a 58k equivalent resistor by the PD I-V amplifiers. These signals are added by the RF summing amplifier, and the photodiode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be performed at this pin.
1k 3.3 32 58k C PD1 36 iPD1 V1 B PD2 37 iPD2 V2 PD2 IV AMP VC VB PD1 IV AMP VC 58k 10k VA 10k
30k RF_M A 31 RF_O
FOK DEFECT RF SUMMING AMP V3
D
The low frequency component of the RFO output voltage is VRFO = - 30k (VA + VB - 2V3) + V3 10k
= -3 {-58k (iPD1 + iPD2) + V1 + V2 - 2V3} + V3, and the setting is V1 = V2 = V3, then VRFO = 174k x (iPD1 + iPD2) + V3
- 16 -
CXA2542AR
Focus Error Amplifier
R3 58k
RF V2 R5 32k
R7 174k
PD2 37 B+D
VB PD2 IV AMP VC R2 58k
48 FE AMP RF V1 R4 32k 1
FEO R10 10k FEI R9 10k C1 2200p GND
PD1 36 A+C
VA PD1 IV AMP VC VCC
R6 174k R1 16k 6 R8 100k FE_O 5 FE_M
GND
x1 x2
x4
x8 x16 x32 VC
FOCUS PHASE COMPENSATION
R11 100k DRIVER
IFB3
IFB5
IFB2
x32 25mV/STEP RESET : IFB1 to IFB6 ON VEE 20mV VIN VC VH
IFB1
IFB4
IFB6
VIN > VH L VIN < VH H FOH
VC 23 SENS1 SENS SELECTOR
FOL VL VIN > VL H VIN < VL L -20mV VC
24 SENS2
The focus error amplifier calculates the difference between outputs VA and VB of the RF I-V amplifier, and outputs current-voltage converted voltage of the photodiode (A + C - B - D). The FEO output voltage: VFEO = = 174k (VA - VB) 32k 174k {(-58k x iPD1) - (-58k x iPD2)} 32k
= 315.4k (iPD2 - iPD1)
The focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment. The focus bias adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF. The 6-bit focus bias adjustment switches are controlled with commands. IFB1 to IFB6 are all ON after a reset. The voltage is varied by approximately 25mV per step.
- 17 -
CXA2542AR
* Focus error amplifier offset adjustment (when adjusting the IC offset) The offset adjustment is performed by comparing the FEO when the focus servo is OFF with the reference level. The FEO and reference level are compared by the window comparator, and the comparison results are output from SENS1 and SENS2. (ADDRESS D11001110D6) Adjust the offset so that SENS1 and SENS2 are both High. Set the reference level to the center 20mV. 25mV < 40mV < 50mV
Reference level width Variable voltage per step Variable voltage per 2 steps
* Focus bias fine adjustment Fine adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF while monitoring a DSP jitter meter with the microcomputer. The 6-bit focus bias adjustment switches are controlled with commands.
- 18 -
CXA2542AR
Tracking Error Amplifier
R23 100k C3 0.01 R24 150k C4 0.01
TEO 41 R2 260k C2 12p F 38 VF VC F I-V AMP R5 13k R3 26k VC R8 17k R4 6.8k R13 13k V R12 96k VC VE VC E I-V AMP TE AMP R16 NORMAL 96k R14 13k TGFL R9 17k GAIN UP GAIN UP TGFL NORMAL R18 15k
GND
GND 42
LPFI VIN > VH L VIN < VH H VH BALH 23 BALL - SENS1
20mV VC VIN VL
+
E 39
C1 12p
TOG1
TOG2
TOG3
TOG4
R17 20k R19 32k R20 15k R21 6.6k R22 3k
R1 260k
VC
VIN > VL H -20mV VIN < VL L SENS VIN > VH L SELECTOR VIN < VH H VH TGH 200mV SENS2 VIN TGL VL 24
VC
CPU
R6 75k R7 BAL1 110k R10 BAL2 56k R11 BAL3 27k R15 BAL4 13k
VC
150mV RE VC
VIN > VL H VIN < VL L 21 COMAND COMAND CONTROL CONTROL 20 19 18 XRST DATA XLT CLK
VC
The difference between E I-V amplifier output VE and F I-V amplifier output VF is taken and output from TEO. The tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based automatic adjustment. The balance adjustment is performed by varying the combined resistance value of the T-configured feedback resistance at the E I-V amplifier. E I-V AMP feedback resistance = R1 + R4 + R1 x R4 RE F I-V AMP feedback resistance = R2 + R5 + R2 x R5 = 403k R3 Vary the combined resistance value of the E I-V amplifier's feedback resistance by using the balance adjustment switches (BAL1 to BAL4). The gain adjustment is performed by resistance dividing the TE AMP output by the gain adjustment switches (TOG1 to TOG4). The balance and gain adjustment switches are controlled with commands. Set the cut-off frequency of the external LPF between 10Hz and 100Hz.
- 19 -
CXA2542AR
* Balance adjustment The balance adjustment is performed by passing the tracking error signal (TEO signal) through the external LPF, extracting the offset DC, and comparing it to the reference level. However, the TEO signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through the LPF leaves lower frequency components, and the complete offset DC can not be extracted. To extract it, monitor the TEO signal frequency at all times, and perform adjustment only when a frequency that can lower a sufficient gain appears on the LPF. Use the C.OUT output to check this frequency. The offset DC and reference level are compared by the window comparator. The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001100D6) Adjust the balance so that the SENS1 and SENS2 pins are both High. VIN < VL < VH SENS1 pin BALH SENS2 pin BALL H L VL < VIN < VH H H VL < VH < VIN L H
VH: High level threshold value VIN: Window comparator input signal VL: Low level threshold value
* Gain adjustment Gain adjustment is performed by passing the TEO signal through the HPF and comparing the AC component to the reference level. The AC component is generated by taking the difference between TE and the offset DC input to Pin 42. The AC component and reference level are compared by the window comparator. The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001101D6) The comparison signal is as follows.
(1) (2) (3)
VH VL VIN SENS1 pin TGH H H
SENS2 pin TGL
L
The gain should be adjusted so that the SENS1 and SENS2 pins are as shown in status (2). When the TEO signal level is low and TGH (SENS1 pin) does not go Low, the gain should be raised with the TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL (SENS2 pin).
- 20 -
CXA2542AR
APC & Laser Power Control
VCC
R1 22
C2 100 LD 34
R6 1k
VCC LDON
L1 10H
130mV PD 35 R8 10k
R10 56k
C1 1
R2 500 LD PD
R3 100 R4 10k R5 55k R11 10k VL R14 12.5k R12 56k VREF VEE
GND VEE VEE MIRR RF_I 30 FOK R7 13k RF_O 31 R9 41k RF VEE VC 670mV
LPC ON/OFF 50%/30%
C3 0.01
0.684V for 4.5V or more 0.57V for 3.6V or less
33
R13 1M VEE VEE
* APC When the laser diode is driven by a constant current, the optical power output has extremely large negative temperature characteristics. The APC circuit is used to maintain the optical power output at a constant level. The laser diode current is controlled according to the monitor photodiode output. * Laser power control The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the RF level fluctuations. The RF_O and RF_I levels are compared and the larger of the two is smoothed by the RFTC's external CR. This signal is then compared with the reference level. The laser power is controlled by attaching an offset to VL according to the results of comparison with the reference level. The reference level is set to 0.57V for the power supply of 3.6V or less and to 0.684V for 4.5V or more. LPC ON/OFF and LD ON/OFF control is performed with commands. The laser power control limit can also be switched between 50% and 17% with commands. LPC OFF ON ON LPCL -- 50% 30% VL variable range Approximately 1.27V Approximately 1.27V 625mV Approximately 1.27V 375mV - 21 -
RFTC
C4 1
CXA2542AR
Center Voltage Generation Circuit (The figure below shows a single voltage application; Connect to GND for dual power supplies.) The maximum current is approximately 3mA. The output impedance is approximately 50.
VCC VCC
30k VC 50 46
VC
30k
VEE Connected internally to the VEE pin.
GND
- 22 -
CXA2542AR
Focus Servo
6k 0.022 47 FEO 48 10k 1 10k 2200p 2 0.1 FDFCT FGD 3 680k 40k 0.1 ISET 16 50k FS2 FLB 4 0.1 FSET 10 510k 0.015 4.7 7 SRCH FS1 Charge up 60k 11 22 50k FE_M 6 100k FEI 100k DFCT FS3 FS4 68k Focus 100k phase Compensation FE_O 5 FE 300k FZC 54k FZC SENS SELECTOR 23 SENS1
FOCUS COIL
The above figure shows a block diagram of the focus servo. Ordinarily the FE signal is input to the focus phase compensation circuit through a 68k resistance; however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal 100k resistance and the capacitance connected to Pin 2. When this DFCT prevention circuit is not used, leave Pin 2 open. The defect switch operation can be enabled and disabled with command. The capacitor connected between Pin 4 and GND is a time constant to boost the low frequency in the normal playback state. The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510k is connected to Pin 10. The focus search level is approximately 1.1Vp-p when using the constants indicated in the above figure. This level is inversely proportional to the resistance connected between Pin 16 and VEE. However, changing this resistance also changes the level of the track jump and sled kick as well. The FZC comparator inverted input is set to 10% of Vcc and VC (Pin 46); (Vcc - VC) x 10%. 510k resistance is recommended for Pin 10.
- 23 -
CXA2542AR
Tracking and Sled Servo
TE
+
41 TEO
-
TGH GAIN TGL WINDOW COMPARATOR BALH BALANCE WINDOW COMPARATOR BALL
SENS SELECTOR
24 SENS2 23 SENS1
100k
150k
BUFFER AMP 42
0.01
0.01
LPFI
TE DFCT TM1 680k 680k TG1
SL_O 15
SLED MOTOR
M
0.015
3.3 22 15k
100k TDFCT 45 100k 66p 14 TM6 22A
SL_M
0.1
TM5 ATSC 1k 1k ATSC 43
TM2 22A 13
SL_P
0.047 47k
330k
470p
0.022 44
TZC TZC 8 TGU TG2 TG2 470k
100k
TM4 11A TM3 11A 90k
82k TA_M 11 100k
20k
0.033 9
Tracking Phase Compensation
10k
TA_O TM7
12
FSET 10 510k 0.015
The above figure shows a block diagram of the tracking and sled servo. The capacitor connected between Pins 8 and 9 is a time constant to cut the high-frequency gain when TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510k resistance is connected to Pin 10. In the CXA2542AQ, TG1 and TG2 are inter-linked switches. To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 11. To be more specific, Track jump peak voltage = TM3 (or TM4) current x feedback resistance value The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 14; Sled kick peak voltage = TM5 (or TM6) current x feedback resistance The values of the current for each switch are determined by the resistance connected between Pin 16 and VEE. When this resistance is 60k : TM3 (or TM4) = 11A, and TM5 (or TM6) = 22A. As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the internal resistance (100k) and the capacitance connected to Pin 45. - 24 -
120k
8.2k
TRACKING COIL
CXA2542AR
The ISET pin is used to connect external resistance. This external resistance sets the current which determines the focus search, track jump, and sled kick levels. * Focus search current I1 =
I1 I2
VBG x R
1 2
(VBG: approximately 1.27V)
I2 = 2I1
FS1
* Track jump current (TM3 and TM4 current) I= VBG x R 1 2
* Sled kick current (TM5 and TM6 current, when D1 = D0 = 0 during 1X$ commands) I= VBG R
Use external resistance of between 30k and 240k. Using external resistance outside this range may cause oscillation.
- 25 -
CXA2542AR
Focus OK Circuit
RF DEFECT RF_O C5 0.01 RF_I 31
x1
VCC
20k V4 44k 25 FOK 56k 0.63V
30 LPC MIRR 15k
VG
FOCUS OK AMP
FOCUS OK COMPARATOR
The focus OK circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the focus OK amplifier output is also obtained. V4 is set in V3=V4 to cancel V3 of the RF amplifier voltage VRFO. The focus OK output is inverted when VRFI - VRFO -0.51V. Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01F selected, the fc is equal to 1kHz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented. Defect circuit After differentiated with the capacitance coupling and then inverted, the RF_O signal is bottom held by means of the long and short time constants. The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms. The long time-constant bottom hold keeps the mirror level prior to the defect and shifts the level. The long and short time-constant signals are compared to generate the mirror defect detection signal. Be sure to disable DFCT ($34X) during focus search because the focus drive waveform is muted.
0.068 CC1 27 FOK a RF
x2
CC2 26 FLIP FLOP b c DFCT2 24 SENS2 SENS SELECTOR
43k
DEFECT AMP
d DFCT1 DEFECT SW 30 CB 0.01 -0.5V DEFECT BOTTOM HOLD DEFECT COMPARATOR f INTERRUPTION COMPARATOR
e
23 SENS1
a
RFO
b
DEFECT AMP
c
BOTTOM HOLD (1) solid line H SENS1 L H INT L
d
BOTTOM HOLD (2) broken line
e
f
- 26 -
CXA2542AR
Mirror Circuit The mirror circuit performs peak and bottom hold after the RFI signal has been inverting amplified. For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation.
FOK RF_O 31 C5 0.01 30 RF_I DEFECT RF FOK LPC
x 1.4
1V 51k MIRROR HOLD AMP 1.5k PEAK & BOTTOM HOLD H
x1
0.033 29 CP
22k J MIRR SENS SELECTOR MIRROR COMPARATOR
G MIRROR AMP
I
K
24 SENS2
RF_O 0V
G (RF_I)
0V
H (PEAK HOLD)
0V
I (BOTTOM HOLD) J K (MIRROR HOLD)
0V
MIRR
H L
The DC restored-envelope signal J is obtained by amplifying the difference between the peak and bottom hold signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal K. If the value of C5 is made smaller, the low frequency component of the RF signal is cut off and the amplification of the signal G gets small. Then, that of the signal J gets also small and the signal K level becomes low, resulting in the short mirror output pulse width. Accordingly, when on the disc track, the mirror output is Low; when between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time constant must be sufficiently large compared with the traverse signal.
- 27 -
CXA2542AR
SENS Selector
FZC DFCT1 TZC BALH 23 SENS1 TGH FOH ATSC
HIGH-Z DFCT2 MIRR BALL 24 SENS2 TGL FOL
What is output to the SENS1 and SENS2 pins varies according to the address input to the DATA pin. DATA (Pin 20) 8-bit transfer ADDRESS D7 0 0 0 0 1 D6 0 0 0 1 1 D5 0 0 1 0 1 D4 0 1 0 0 1 D3 X X X X X DATA D2 X X X X X D1 X X X X X D0 X X X X X FZC DFCT1 TZC H (HIGH-Z) H (HIGH-Z) DFCT2 MIRR H (HIGH-Z) SENS1 SENS2
DATA (Pin 20) 12-bit transfer ADDRESS D11 D10 0 0 0 0 0 0 0 0 D9 1 1 1 1 D8 1 1 1 1 D7 0 0 1 1 D6 0 1 0 1 D5 X X X X D4 X X X X DATA D3 X X X X D2 X X X X D1 X X X X D0 X X X X BALH TGH FOH ATSC BALL TGL FOL H (HIGH-Z) SENS1 SENS2
Notes) * 12-bit transfer should be performed during $3XX commands. When 8 bits are transferred, SENS1 and SENS2 are switched according to the D3 and D2 data. * SENS1 and SENS2 are switched without latching.
- 28 -
CXA2542AR
Commands The input data to operate this IC is configured as 8-bit/12-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F/$XXX for 12-bit. Commands for the CXA2542AR can be broadly divided into four groups ranging in value from $0X, $1X, $2X, $3XX. 1. $0X (FZC at SENS1 pin (Pin 23), H (Hi-Z) at SENS2 pin (Pin 24)) These commands are related to the focus servo control. The bit configuration is as shown below. D7 0 D6 0 D5 0 D4 0 D3 FS4 D2 -- D1 FS2 D0 FS1
Four focus related switches exist: FS1, FS2, FS4 and DFCT. $00 $02 When FS1 = 0, Pin 7 is charged to (22A - 11A) x 50k = 0.55V. If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 5 becomes 0V. From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output to Pin 5. This voltage level is obtained by equation 1 below. (22A - 11A) x 50k x resistance between Pins 5 and 6 .... Equation 1 50k
$03
The SRCH DOWN speed can be increased by the charge up circuit. From the state described above, FS1 becomes 1, and a current source of +22A is split off. Then, a CR charge/discharge circuit is formed, and the voltage at Pin 7 decreases with the time as shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 7 when FS1 goes from 0 1 This time constant is obtained with the 50k resistance and an external capacitor. By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 5)
- 29 -
CXA2542AR
1-1. FS4 This switch is provided between the focus error input and the focus phase compensation, and is in charge of turning the focus servo ON and OFF. $00 $08 Focus off Focus on 1-2. Procedure of focus activation For description, suppose that the polarity is as described below. a) The lens is searching the disc from far to near; b) The output voltage (Pin 5) is changing from negative to positive; and c) The focus S-curve is varying as shown below.
A t
Fig. 3. S-curve The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and turning the focus servo switch ON are performed while the focus S-curve transits the point A indicated in Fig. 3. To prevent misoperation, this signal is ANDed with the focus OK signal. In this IC, the FZC (Focus Zero Cross) signal is output from the SENS1 pin (Pin 23) as the point A transit signal. In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case). Following the line of the above description, focusing can be well obtained by observing the following timing chart.
(20ms) (200ms) $02 ($00) $03 $08
Drive voltage
Focus error
The broken lines in the figure indicate the voltage assuming the signal not in focus.
SENS1 (FZC) The instant when the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart - 30 -
CXA2542AR
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ? NO YES
Transfer $08
F. OK? NO YES Transfer $08
F. OK? NO YES FZC ? NO YES
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences
2. $1X (DFCT1 at SENS1 pin (Pin 23), DFCT2 at SENS2 pin (Pin 24)) These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output. The bit configuration is as follows: D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0
D1 (PS1) 0 0 1 1
D0 (PS0) 0 1 0 1
TG1, TG2 Brake circuit ON/OFF ON/OFF
Sled kick level
TG1, TG2, TM7 The purpose of TG1 and TG2 is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump. For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the tracking error is 180 out-of-phase to cut the unneeded portion of the tracking error and apply braking.
- 31 -
Relative value 1 2 3 4
Sled kick level
CXA2542AR
[A] RF_I 30 [D] TZC 44 Waveform Shaping Envelope Detection
[B] Waveform Shaping [E] Edge Detection (MIRR) [C] [F] (Latch) [G]
D2 TM7 Low: open High: make [H]
DQ CK
BRK
CXA2542AR
Fig. 6. TM7 movement during braking operation
From inner to outer track [A] [B] [C] [D] [E] [F] [G] [H]
From outer to inner track
("MIRR")
("TZC")
0V
Braking is applied from here.
Fig. 7. Internal waveform 3. $2X (TZC at SENS1 pin (Pin 23), MIRR at SENS2 pin (Pin 24)) These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse and fast forward pulse during access operations. D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0
Tracking control 00 off 01 Servo ON 10 F-JUMP 11 R-JUMP TM1, TM3, TM4,
Sled control 00 off 01 Servo ON 10 F-FAST FORWARD 11 R-FAST FORWARD TM2, TM5, TM6
- 32 -
CXA2542AR
4. $3XX These commands mainly control the balance and gain control circuit switches used during automatic tracking adjustment and the bias circuit switch used during automatic focus bias adjustment. In the initial resetting state, BAL1 to BAL4 switches and TOG1 to TOG4 switches are ON. Also, the IFB1 to IFB6 switches are ON. * Balance adjustment The balance adjustment switches BAL1 to BAL4 can be controlled by setting D6 = 0 and D7 = 0. The switches are set using D0 to D3. At this time, SENS1 outputs BALH and SENS2 outputs BALL. Data is set by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 0 and D7 = 0. Sending a latch pulse with D6, D7 0 does not change the balance switch settings.
START
BAL1 to BAL4 Switch Control
C.OUT is the frequency high enough ? YES SENS1/2 Balance OK ?
NO
Adjustment Completed
Balance adjustment * Gain adjustment The gain adjustment switches TOG1 to TOG4 can be controlled by setting D6 = 1 and D7 = 0. These switches are set using D0 to D3. At this time, SENS1 outputs TGH and SENS2 outputs TGL. In a fashion similar to the method used with the balance adjustment, set the data by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 1 and D7 = 0.
START
TOG1 to TOG4 Switch control SENS1/2 GAIN OK ? NO YES Adjustment Completed
Gain adjustment - 33 -
CXA2542AR
* Focus bias adjustment The focus bias adjustment switches IFB1 to IFB6 can be controlled by setting D6 = 0 and D7 = 1. The switches are set using D0 to D5. At this time, SENS1 outputs FOH and SENS2 outputs FOL. Data is set by specifying switch conditions D0 to D5 and sending a latch pulse with D6 = 0 and D7 = 1.
START
IFB1 to IFB6 Switch Control SENS1/2 BIAS OK ? YES Adjustment Completed
NO
Focus bias adjustment method
* TGFL The tracking gain can be switched by setting D5 with D6 = 1 and D7 = 0. The tracking gain is GAIN UP with D5 = 1 and NORMAL GAIN with D5 = 0. The TEO signal level can be made higher by approximately 6dB for GAIN UP. When the TEO signal level is low and TGH (SENS1 pin) does not go Low during tracking adjustment, the gain should be raised with the TGFL command for adjustment. * LPC The laser power control circuit can be turned ON and OFF by setting D0 with D6 = 1 and D7 = 1. The circuit is ON with D0 = 1 and OFF with D0 = 0. * LPCL The laser power control limit can be switched between 30% and 50% by setting D1 with D6 = 1 and D7 = 1. The control limit is 30% with D1 = 0 and 50% with D1 = 1. * LDON The laser diode can be turned ON and OFF by setting D2 with D6 = 1 and D7 = 1. The laser diode is ON with D2 = 1 and OFF with D2 = 0.
- 34 -
CXA2542AR
* ATSC The anti-shock function can be controlled by setting D3 with D6 = 1 and D7 = 1. This function is disabled with D3 = 1 and enabled with D3 = 0. At this time, SENS1 outputs ATSC. Even if ATSC is disabled, ATSC is output to SENS1. When an anti-shock signal is generated during the enable status, TG1 and TG2 switch to GAIN UP mode. (In the Block Diagram, TG1 is set to the side and TG2 is OFF. Even if TG1 and TG2 are in NORMAL mode, they switch to GAIN UP mode in conjunction with ATSC.) When the anti-shock function is not used, Pin 43 (ATSC) should be connected to VC. * RDFCT2 DFCT2 can be reset by setting D4 with D6 = 1 and D7 = 1. DFCT2 is reset with D4 = 1. After a reset, High is held when DFCT1 rises. During $1X commands, DFCT2 is output from SENS2. DFCT2 operates even if DFCT is disabled. Whether or not DFCT rises at the proper timing for the microcomputer can also be confirmed. * INT The interruption (scratched disc) countermeasure circuit can be set to the operating status by setting D5 with D6 = 1 and D7 = 1. This circuit is enabled when D5 = 1 and disabled when D5 = 0. Even if DFCT1 does not rise, this circuit is effective for scratched discs which cause MIRR to rise. When MIRR rises, the DFCT switch is routed through the low-pass filter. The interruption countermeasure circuit is forcibly turned OFF regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC) Even if DFCT is disabled, the interruption countermeasure circuit operates when INT is enabled.
- 35 -
CXA2542AR
CPU Serial Interface Timing Chart
DATA D0 tWCK CLK 1/fck tD tWL tCD D1 D2 tWCK D3 tSU D4 th D5 D6 D7 D0
XLT
(VCC = 3.0V) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width Data transfer interval Low level input voltage High level input voltage Symbol fck fwck 500 500 500 500 1000 1000 0.0 (VCC - VEE) x 0.9 (VCC - VEE) x 0.1 VCC Min. Typ. Max. 1 Unit MHz ns ns ns ns ns ns V V
tsu th tD tWL tCD
VIL VIH
- 36 -
System Control DATA (Pin 20) 8-bit transfer DATA SENS1 D1 D0 SENS2 D3 D2
Item
ADDRESS
D7
D6
D5
D4
FOCUS CONTROL -- FZC H (HIGH-Z) TG1, TG2 BRAKE 1 = ENABLE 0 = DISABLE SLED MODE 2 TZC DFCT1 DFCT2 SLED KICK + 2 SLED KICK + 1 1 = GAIN UP 0 = NORMAL TRACKING MODE 1
0
0
0
0
FS4 Focus 1 = ON 0 = OFF FS2 SRCH ON 1 = ON 0 = OFF FS2 SRCH UP 1 = UP 0 = DOWN
TRACKING CONTROL
0
0
0
1
TRACKING SLED MODE
0
0
1
0
MIRR
- 37 - D1 OFF ON FWD MOVE REV MOVE 1 1 1 0 0 1 0 0 D0
1 TRACKING MODE
2 SLED MODE
D3
D2
OFF
0
0
ON
0
1
FWD JUMP
1
0
REV JUMP
1
1
CXA2542AR
DATA (Pin 20) 12-bit transfer DATA SENS1 D2 BAL3 1 = OFF 0 = ON TOG3 1 = OFF 0 = ON IFB3 1 = OFF 0 = ON LDON LPCL 1 = 50% 0 = 30% 1 = OFF 0 = ON IFB2 IFB1 1 = OFF 0 = ON LPC 1 = ON 0 = OFF ATSC H (HIGH-Z) FOH FOL 1 = OFF 0 = ON 1 = OFF 0 = ON TOG2 TOG1 TGH TGL 1 = OFF 0 = ON 1 = OFF 0 = ON BALH BAL2 BAL1 BALL D1 D0 SENS2 D5 DFCT BAL4 -- 1 = OFF 0 = ON TOG4 -- 1 = OFF 0 = ON IFB4 1 = OFF 0 = ON ATSC 0 1 = DISABLE 0 = ENABLE TGFL 1 1 = GAIN UP 0 = NORMAL IFB6 IFB5 1 = OFF 0 = ON RDFCT2 0 1 = OFF 0 = ON INT 1 1 = ENABLE 1 = RESET 1 = DISABLE 1 = ON 0 = DISABLE 0 = NORMAL 0 = ENABLE 0 = OFF D4 D3
Item
ADDRESS
D11 D10 D9
D8 D7
D6
E-F BALANCE
0
0
1
1
0
TRACKING GAIN
0
0
1
1
0
FOCUS BIAS
0
0
1
1
1
- 38 -
Others
0
0
1
1
1
Notes) * When ATSC is enabled, even if TG1 and TG2 are in NORMAL mode, TG1 and TG2 switch to GAIN UP mode in conjunction with ATSC. * INT is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC) When reset * SENS1 = FZC * SENS2 = High (Hi-Z) * RDFCT2 = 1 (Reset) * IFB1 to IFB6 = 0 (switch ON) * TOG1 to TOG4 = 0 (switch ON) * BAL1 to BAL4 = 1 (switch ON) * Other data is "0".
CXA2542AR
CXA2542AR
Serial Data Truth Table Serial Data FOCUS CONTROL 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F HEX FS4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Functions FS2 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes) * FS1 1: OFF 0: ON * FS2 1: ON 0: OFF * FS4 In the Block Diagram: 1: SW side 0: SW side
BRAK SLD KICK TRACKING CONTROL 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0001 0111 0001 1000 0001 1001 0001 1010 0001 1011 0001 1100 0001 1101 0001 1110 0001 1111 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F TG1 Fig. 6 KICK KICK TG2 D2 +2 +1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes) * TG1 In the Block Diagram: 1: SW side 0: SW side * TG2 1: OFF 0: ON * BRAKE When D2 in Fig. 6 is: 1: 1 0: 0 * Sled kick level D1 0 0 1 1 D0 0 1 0 1 Relative value 1 2 3 4
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CXA2542AR
Serial Data TRACKING/SLED MODE 0010 0000 0010 0001 0010 0010 0010 0011 0010 0100 0010 0101 0010 0110 0010 0111 0010 1000 0010 1001 0010 1010 0010 1011 0010 1100 0010 1101 0010 1110 0010 1111
HEX
Function TM6 TM5 TM4 TM3 TM2 TM1
$20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
Notes) * TM1/TM2 In the Block Diagram: 1: SW side 0: SW side * TM3/TM4/TM5/TM6 1: ON 0: OFF
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CXA2542AR
Serial Data $3XX 0011 0000 0000 0011 0000 0001 0011 0000 0010 0011 0000 0011 0011 0000 0100 0011 0000 0101 0011 0000 0110 0011 0000 0111 0011 0000 1000 0011 0000 1001 0011 0000 1010 0011 0000 1011 0011 0000 1100 0011 0000 1101 0011 0000 1110 0011 0000 1111 0011 0001 0000 0011 0001 0001 0011 0001 0010 0011 0001 0011 0011 0001 0100 0011 0001 0101 0011 0001 0110 0011 0001 0111 0011 0001 1000 0011 0001 1001 0011 0001 1010 0011 0001 1011 0011 0001 1100 0011 0001 1101 0011 0001 1110 0011 0001 1111 0011 0010 0000 0011 0010 0001 0011 0010 0010 0011 0010 0011 0011 0010 0100 0011 0010 0101 0011 0010 0110 0011 0010 0111 0011 0010 1000 0011 0010 1001 0011 0010 1010 0011 0010 1011 0011 0010 1100 0011 0010 1101 0011 0010 1110 0011 0010 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
INT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RDF ATSC LDON LPCL LPC DFCT CT2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E D D D D D D D D D D D D D D D D
$300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F $320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32A $32B $32C $32D $32E $32F
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- --------
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CXA2542AR
Serial Data $3XX 0011 0011 0000 0011 0011 0001 0011 0011 0010 0011 0011 0011 0011 0011 0100 0011 0011 0101 0011 0011 0110 0011 0011 0111 0011 0011 1000 0011 0011 1001 0011 0011 1010 0011 0011 1011 0011 0011 1100 0011 0011 1101 0011 0011 1110 0011 0011 1111 0011 0100 0000 0011 0100 0001 0011 0100 0010 0011 0100 0011 0011 0100 0100 0011 0100 0101 0011 0100 0110 0011 0100 0111 0011 0100 1000 0011 0100 1001 0011 0100 1010 0011 0100 1011 0011 0100 1100 0011 0100 1101 0011 0100 1110 0011 0100 1111 0011 0101 0000 0011 0101 0001 0011 0101 0010 0011 0101 0011 0011 0101 0100 0011 0101 0101 0011 0101 0110 0011 0101 0111 0011 0101 1000 0011 0101 1001 0011 0101 1010 0011 0101 1011 0011 0101 1100 0011 0101 1101 0011 0101 1110 0011 0101 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
INT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RDF ATSC LDON LPCL LPC DFCT CT2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D D D D D D D D D D D D D D D D -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$330 $331 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F $340 $341 $342 $343 $344 $345 $346 $347 $348 $349 $34A $34B $34C $34D $34E $34F $350 $351 $352 $353 $354 $355 $356 $357 $358 $359 $35A $35B $35C $35D $35E $35F
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- --------
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CXA2542AR
Serial Data $3XX 0011 0110 0000 0011 0110 0001 0011 0110 0010 0011 0110 0011 0011 0110 0100 0011 0110 0101 0011 0110 0110 0011 0110 0111 0011 0110 1000 0011 0110 1001 0011 0110 1010 0011 0110 1011 0011 0110 1100 0011 0110 1101 0011 0110 1110 0011 0110 1111 0011 0111 0000 0011 0111 0001 0011 0111 0010 0011 0111 0011 0011 0111 0100 0011 0111 0101 0011 0111 0110 0011 0111 0111 0011 0111 1000 0011 0111 1001 0011 0111 1010 0011 0111 1011 0011 0111 1100 0011 0111 1101 0011 0111 1110 0011 0111 1111 0011 1000 0000 0011 1000 0001 0011 1000 0010 0011 1000 0011 0011 1000 0100 0011 1000 0101 0011 1000 0110 0011 1000 0111 0011 1000 1000 0011 1000 1001 0011 1000 1010 0011 1000 1011 0011 1000 1100 0011 1000 1101 0011 1000 1110 0011 1000 1111
HEX
BAL SW TOG SW 43214321
TGFL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
INT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RDF ATSC LDON LPCL LPC DFCT CT2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$360 $361 $362 $363 $364 $365 $366 $367 $368 $369 $36A $36B $36C $36D $36E $36F $370 $371 $372 $373 $374 $375 $376 $377 $378 $379 $37A $37B $37C $37D $37E $37F $380 $381 $382 $383 $384 $385 $386 $387 $388 $389 $38A $38B $38C $38D $38E $38F
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- --------
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- --
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CXA2542AR
Serial Data $3XX 0011 1001 0000 0011 1001 0001 0011 1001 0010 0011 1001 0011 0011 1001 0100 0011 1001 0101 0011 1001 0110 0011 1001 0111 0011 1001 1000 0011 1001 1001 0011 1001 1010 0011 1001 1011 0011 1001 1100 0011 1001 1101 0011 1001 1110 0011 1001 1111 0011 1010 0000 0011 1010 0001 0011 1010 0010 0011 1010 0011 0011 1010 0100 0011 1010 0101 0011 1010 0110 0011 1010 0111 0011 1010 1000 0011 1010 1001 0011 1010 1010 0011 1010 1011 0011 1010 1100 0011 1010 1101 0011 1010 1110 0011 1010 1111 0011 1011 0000 0011 1011 0001 0011 1011 0010 0011 1011 0011 0011 1011 0100 0011 1011 0101 0011 1011 0110 0011 1011 0111 0011 1011 1000 0011 1011 1001 0011 1011 1010 0011 1011 1011 0011 1011 1100 0011 1011 1101 0011 1011 1110 0011 1011 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
INT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RDF ATSC LDON LPCL LPC DFCT CT2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$390 $391 $392 $393 $394 $395 $396 $397 $398 $399 $39A $39B $39C $39D $39E $39F $3A0 $3A1 $3A2 $3A3 $3A4 $3A5 $3A6 $3A7 $3A8 $3A9 $3AA $3AB $3AC $3AD $3AE $3AF $3B0 $3B1 $3B2 $3B3 $3B4 $3B5 $3B6 $3B7 $3B8 $3B9 $3BA $3BB $3BC $3BD $3BE $3BF
-- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- --
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CXA2542AR
Serial Data $3XX 0011 1100 0000 0011 1100 0001 0011 1100 0010 0011 1100 0011 0011 1100 0100 0011 1100 0101 0011 1100 0110 0011 1100 0111 0011 1100 1000 0011 1100 1001 0011 1100 1010 0011 1100 1011 0011 1100 1100 0011 1100 1101 0011 1100 1110 0011 1100 1111 0011 1101 0000 0011 1101 0001 0011 1101 0010 0011 1101 0011 0011 1101 0100 0011 1101 0101 0011 1101 0110 0011 1101 0111 0011 1101 1000 0011 1101 1001 0011 1101 1010 0011 1101 1011 0011 1101 1100 0011 1101 1101 0011 1101 1110 0011 1101 1111 0011 1110 0000 0011 1110 0001 0011 1110 0010 0011 1110 0011 0011 1110 0100 0011 1110 0101 0011 1110 0110 0011 1110 0111 0011 1110 1000 0011 1110 1001 0011 1110 1010 0011 1110 1011 0011 1110 1100 0011 1110 1101 0011 1110 1110 0011 1110 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
INT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RDF ATSC LDON LPCL LPC DFCT CT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E E E E E E E E D D D D D D D D E E E E E E E E D D D D D D D D E E E E E E E E D D D D D D D D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$3C0 $3C1 $3C2 $3C3 $3C4 $3C5 $3C6 $3C7 $3C8 $3C9 $3CA $3CB $3CC $3CD $3CE $3CF $3D0 $3D1 $3D2 $3D3 $3D4 $3D5 $3D6 $3D7 $3D8 $3D9 $3DA $3DB $3DC $3DD $3DE $3DF $3E0 $3E1 $3E2 $3E3 $3E4 $3E5 $3E6 $3E7 $3E8 $3E9 $3EA $3EB $3EC $3ED $3EE $3EF
-- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- --
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CXA2542AR
Serial Data $3XX 0011 1111 0000 0011 1111 0001 0011 1111 0010 0011 1111 0011 0011 1111 0100 0011 1111 0101 0011 1111 0110 0011 1111 0111 0011 1111 1000 0011 1111 1001 0011 1111 1010 0011 1111 1011 0011 1111 1100 0011 1111 1101 0011 1111 1110 0011 1111 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
INT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RDF ATSC LDON LPCL LPC DFCT CT2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 E E E E E E E E D D D D D D D D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$3F0 $3F1 $3F2 $3F3 $3F4 $3F5 $3F6 $3F7 $3F8 $3F9 $3FA $3FB $3FC $3FD $3FE $3FF
-- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- --
Notes) * 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values of each bit for serial data. * "--" in the Truth Table indicates that the status does not change. * TGFL In the Block Diagram: 1: SW side 0: SW side * ATSC E: enable/D: disable * DFCT E: enable/D: disable
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CXA2542AR
Initial State (resetting state) Item FOCUS CONTROL TRACKING CONTROL TRACKING SLED MODE ADDRESS DATA HEX $00 $10 $20
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Item E-F BALANCE TRACKING GAIN FOCUS BIAS Others
ADDRESS
DATA
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HEX $300 $340 $380 $3D0
The above data means the following operation modes. FOCUS CONTROL TRACKING CONTROL TRACKING SLED MODE E-F BALANCE TRACKING GAIN FOCUS BIAS Others : FOCUS OFF, FOCUS SEARCH OFF, FOCUS SEACH DOWN : TG1-TG2 NORMAL, BRAKE DISABLE, SLED KICK relative level value 1 : TRACKING OFF, SLED OFF : BAL1 to BAL4 = 0 (switch ON). DFCT ENABLE : TOG1 to TOG4 = 0 (switch ON), TGFL NORMAL : IFB1 to IFB6 = 0 (switch ON) : INT DISABLE, DFCT2 RESET, ATSC ENABLE, LDON OFF, LPCL 30%, LPC OFF
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CXA2542AR
Notes on Operation 1. Focus OK circuit 1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the mirror amplifier HPF. 2) The equivalent circuit for the output pin (FOK) is shown in the diagram below.
VCC 20k FOK 40k 25 RL 100k VCC VEE VEE
The FOK and comparator output are as follows: Output voltage High : VFOKH near Vcc Output voltage Low : VFOKL Vsat (NPN) + VEE
2. Sled amplifier The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB. 3. Focus/Tracking internal phase compensation and reference design material Item FCS 1.2kHz gain 1.2kHz phase 1.2kHz gain TRK 1.2kHz phase 2.7kHz gain 2.7kHz phase 08 08 25 25 25 13 25 13 13 CTGU = 0.1F SD Measurement pin 6 Conditions CFLB = 0.1F CFGD = 0.1F Typ. 21.5 63 13 -125 26.5 -130 Unit dB deg dB deg dB deg
4. Laser Poser Control The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the RF level fluctuations. The laser life is shortened by increasing the laser power when the less light is reflected from the disc. It is recommended that the typical laser power value is set lower to maintain the laser life. Take care of the laser maximum ratings when using the laser power control circuit.
- 48 -
CXA2542AR
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
B
(0.22)
+ 0.05 0.127 - 0.02 0.13 M
0.1 0.1 0.1
0.5 0.2
S
(0.127) +0.05 0.127 - 0.02
(0.18)
0.18 0.03
0 to 10
0.5 0.2
DETAIL B:SOLDER DETAIL A
DETAIL B:PALLADIUM
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
- 49 -
0.127 0.04
+ 0.08 0.18 - 0.03

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